1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more specifically, to a semiconductor integrated circuit device suitable for automatic design and having interconnection layout superior in area efficiency and to a method of arrangement and interconnection of circuit cells (functional circuit blocks) which are the components of the device.
2. Description of the Background Art
In a large scale semiconductor integrated circuit device, not less than 10.sup.8 transistor elements are formed on one chip. In such a large scale device, arrangement and interconnection of transistor elements on the chip come to be extremely complicated, and hence computer aided design is used in order to design circuit device efficiently in short period of time for development. In such computer aided design, functional circuit blocks each implementing prescribed function are arranged, and thereafter, there is a step of arranging interconnections for transmitting signals to each of the functional circuit blocks.
FIG. 77 schematically shows a whole structure of a semiconductor integrated circuit device. FIG. 77 shows a dynamic random access memory (DRAM) as an example of a semiconductor integrated circuit device.
Referring to FIG. 77, the DRAM includes four memory arrays MA1, MA2, MA3 and MA4. Though not explicitly shown, each of the memory arrays MA1 to MA4 includes a plurality of memory cells arranged in rows and columns. Between memory arrays MA1 and MA3, a peripheral circuit block PH1 is arranged, and between memory arrays MA2 and M4, a peripheral circuit block PH2 is arranged. Between memory arrays MA1 and MA2, a peripheral circuit block PH3 is arranged, and between memory arrays MA3 and MA4, peripheral circuit block PH4 is arranged. Functions to be implemented by peripheral circuit blocks PH1 to PH4 are determined dependent on internal structures of memory arrays MA1 to MA4, and the functions include a control for controlling various control signals, row selecting operation and column selecting operation in memory arrays MA1 to MA4, and data input/output operation in accordance with externally applied signals. These peripheral circuit blocks PH1 to PH4 may include a circuit for generating a prescribed internal voltage.
Upon these peripheral circuit blocks PH1 to PH4, circuit layout utilizing automatic arrangement interconnection will be described, taking a small peripheral circuit PHB included in peripheral circuit block PH1 shown in FIG. 77 as an example.
FIG. 78 schematically shows the structure of the small peripheral circuit block PHB shown in FIG. 77. Referring to FIG. 77, the small peripheral circuit block PHB includes two circuit cell bands KCA and KCB. Circuit cell band KCA includes circuit cells CCAa to CCAz as functional circuit blocks, and circuit cell band KCB includes circuit cells CCBa to CCBr. Each of the circuit cells CCAa to CCAz and CCBa to CCBr has its size determined dependent on the function implemented by itself, and serves as a design unit or functional unit implementing the prescribed function. Generally, in layout, circuit cells CCAa to CCaz and CCBa to CCBr are designed respectively, and these are arranged alignedly along one line (linear array) (X direction in FIG. 78). Here, X and Y directions refer to horizontal and vertical directions in FIG. 78. However, these are not directly related to the X (row) and Y (column) directions generally used in a dynamic random access memory. It is simply defined that a direction along which the circuit cells are aligned is X direction (first direction) and a direction orthogonally crossing the X direction is Y direction (second direction).
Between circuit cell bands KCA and KCB, a line band LB in which inter-cell lines for transmitting signal between circuit cell is provided. In the line band LB, lines (main lines) extending along the X direction are arranged. In FIG. 78, line band LB is shown including main lines La to Le. In a direction orthogonal to the main lines La to Le, sub lines Ha to Hj for transmitting signals on main lines La to Le to the circuit cell are arranged. The main lines La to Le and sub lines Ha to Hj belong to different interconnection layers. By physically connecting main lines La to Le included in line band LB to sub lines Ha to Hj through connection holes (contact holes, through holes or via holes), interconnection between circuit cells is established. Here "physically connect" means "forming a connection allowing propagation of electrical signal", and hence physical connection may be "indirective connection through another line such as a barrier metal."
FIG. 79 shows, in enlargement, the structure of the circuit cell portions shown in FIG. 78. FIG. 79 shows two circuit cells CC1 and CC2 as representative. In regions (line regions) adjacent to circuit cells CC1 and CC2 along the Y direction, line bands LB1 and LB2 are arranged. Line band LB1 is shown including main lines L1 and L2, and line band LB2 is shown including a main line L3.
In order to transmit a signal transmitted on main line L1 to circuit cell CC1, a sub line H1 is arranged, and to transmit a signal on main line L3 to circuit cell CC2, a sub line H2 is arranged. These sub lines H1 and H2 are both arranged along the Y direction. Sub line H1 is physically connected to main line L1 through a connection hole V1, and sub line H2 is connected to main line L3 through a connection hole V3. In FIG. 79, a signal transmitted on sub line H1 is shown input to an input portion of a gate circuit g1 included in circuit cell CC1. An output from gate circuit (inverter circuit g1 is applied to one input of a gate circuit (NAND circuit) g2. A line for transmitting the signal from the sub line H1 to the input portion of gate circuit g1 is implemented by an internal line in circuit cell CC1. The internal line of the circuit cell includes a line belonging to the same interconnection layer as the sub line.
In order to transmit operational voltage to circuit cells CC1 and CC2 as well as to circuit cells not shown, a power supply line VCC and a ground line GND are arranged extending along the X direction across the circuit cells CC1 and CC2. The power supply line VCC and the ground line GND are formed in the same interconnection layer as the main lines L1 to L3 included in the line bands LB1 and LB2. Generally, in a semiconductor memory device such as a dynamic random access memory, lines (main lines L1 to L3 and power supply line VCC and ground line GND) extending in the X direction are formed in a second layer of aluminum interconnection layer, while lines (sub lines H1 and H2) extending along the Y direction are formed in a first layer of aluminum interconnection existing below the second layer of aluminum interconnection. Since the second layer aluminum interconnection has smaller number of heat treatment cycles and smaller stress as compared with the first layer of aluminum interconnection, purity of aluminum is made higher, and hence the second layer of aluminum interconnection has smaller electrical resistance and superior electrical property as compared with the first layer of aluminum interconnection layer. Therefore, the second layer of aluminum interconnection is used for the lines transmitting signals over longer distance. For the sub lines which has only to transmit signals over a short distance, the first layer of aluminum interconnection having superior electrical property to a polysilicon interconnection is used.
When a signal is to be transmitted from a main line included in one line band LB1 to another line band LB2 or to a circuit cell band different from the circuit cell band including circuit cells CC1 and CC2, such sub lines cannot be arranged on a circuit cell region (since internal lines in the circuit cells belongs to the same interconnection layer as the sub lines). Therefore, in such a case, a region on which a transistor element is not formed, that is, a feed through region FTR must be provided between circuit cells CC1 and CC2, so that the sub line is arranged through the feed through region FTR. A line arranged in such a feed through region is referred to as a feed through FT. The feed through region FTR conventionally represents only a region between circuit cells adjacent in the column direction (X direction) of the circuit cells, and it does not include the region on which a line band is arranged. By the provision of the feed through region, a line (feed through FT) satisfying the condition that a line extending in the Y direction is formed by using the first layer of aluminum interconnection can be arranged.
FIG. 80 shows a structure near the feed through region. FIG. 80 shows a feed through FT arranged adjacent to one circuit cell CC included in one circuit cell band KC. The circuit cell CC includes a p channel MOS transistor forming (arrangement) region PT on which only a p channel MOS transistor (insulated gate type field effect transistor) is formed (arranged) and an n channel MOS transistor forming (arrangement) region NT on which an n channel MOS transistor is formed (arranged). FIG. 80 shows one p channel MOS transistor PM and one n channel MOS transistor NM as representative. The p channel transistor forming region PT and the n channel transistor forming region NT are arranged extending along the X direction in circuit cell band KC. Parallel to p channel transistor forming region PT, a power supply line VCC, which is formed in the second layer of aluminum interconnection is arranged, and on the n channel transistor forming region NT, a ground line GND which is formed in the second layer of aluminum interconnection, is arranged.
On both sides of the circuit cell CC (in Y direction), line bands LBA and LBB are arranged. Main line La1 of line band LBA and main line Lb3 of line band LBB are mutually connected by sub line Ha. Main line La1 is connected to sub line Ha through a via hole V4, and main line Lb3 is connected to sub line Ha through via hole V5. The p channel MOS transistor PM has its source region SP connected to the power supply line VCC, while the n channel MOS transistor NM has its source region SN connected to the ground line GND. Drain region DP of p channel MOS transistor PM and drain region DN of n channel MOS transistor NM are interconnected by means of an inner line IH formed in the first layer of aluminum interconnection.
Parallel to the sub line Ha and to inner line IH, a feed through FT formed by the first layer of aluminum interconnection is arranged along the Y direction. The feed through FT is physically connected to main line Lb2 included in line band LBB by means of a via hole V6. These MOS transistors PM and NM constitute an inverter.
FIG. 81 schematically shows a cross section of the p channel MOS transistor PM shown in FIG. 80 along a line A-A'. Referring to FIG. 81, the source region SP of p channel MOS transistor PM includes an impurity diffusion region D1 formed at a surface of a semiconductor substrate (or in a well region), and an intermediate connection layer AI constituted in the first layer of aluminum interconnection which is physically connected to impurity diffusion region D1. The intermediate connection layer AI is also connected to the power supply line VCC by means of another contact. By connecting the source impurity diffusion region D1 to the power supply line VCC through the intermediate connection layer AI, aspect ratio at the contact portion is improved.
Drain region DP includes an impurity diffusion region D2 formed at a surface of the semiconductor substrate (or in a well region). Impurity diffusion region D2 is connected to an inner line IH through a contact. Intermediate connection layer AI and inner line IH are formed in the first layer of aluminum interconnection. Sub line Ha and feed through FT are also formed in the first layer of aluminum interconnection. Therefore, the feed through FT cannot be arranged in a region where a transistor element is formed. Therefore, it is necessary to arrange a feed through region between the circuit cells, which means that there exists a region in the circuit cell band where a circuit cell cannot be arranged. This results in the problem of increased area occupied by the circuit cell band.
When a feed through is to be connected to an internal node of a circuit cell and there is not an object circuit cell (to which a signal is transmitted) in the direction of extension of the feed through, it becomes necessary to provide a line L15 for changing substantial position (in Y direction) of the feed through FT in the line band (line band LBA in FIG. 82), as shown in FIG. 82. The reason for this is that according to the conventional design rule, connection holes other than the connection holes (through hole or via hole: both are used for the same meaning) for the interconnection of inner lines in a circuit cell must be provided in the line band, as will be described later. Therefore, when a signal transmitted on feed through FT is to be transmitted to an input portion of gate circuit g10 in circuit cell CC1 as shown in FIG. 82, the feed through FT is connected to gate circuit g10 by means of through hole V10 in line band LBA, line L15, through hole V11 and sub line H10. Therefore, in line band LBA, a line L15 which is used only for changing the substantial position of the feed through FT is provided in addition to the main lines L10 and L11 which are used for connection between circuit cells, so that area occupied by line band LBA in Y direction is increased. Increase in the area of occupation in Y direction by line band LBA results in increased area of occupation of the circuit formed in accordance with this circuit cell method, whereby a circuit having small area of occupation cannot be formed and higher degree of integration is hindered.
FIG. 83 schematically shows a whole structure of a conventional automatic interconnection-arrangement apparatus. Referring to FIG. 83, the automatic interconnection-arrangement apparatus includes an input device 1 for inputting data to be processed and a command or the like indicating a process to be executed, a processing portion 2 for performing a prescribed process in accordance with the data and the command input through input device 2, a display device 3 displaying necessary information under the control of processing portion 2, and a data memory 4 for storing data input through input device 1 and data generated in the process performed by the processing portion 2. The input device 1 may be any device having a function of inputting information, such as a keyboard, a mouse or a light pen. Input device 1, processing portion 2 and display device 3 are connected to each other by means of a data bus 5.
Processing portion 2 includes a control portion 21 for executing necessary processing, and a program memory 23 for storing information such as rules for interconnection and arrangement, procedure for executing interconnection and arrangement. Control portion 21 is connected to data bus 5 by means of an interface 22. Data memory 4 may be a disk device using a magnetic recording medium, or an external memory device such as an RAM disk. Processing operation of the device shown in FIG. 83 when information is input will be described with reference to FIGS. 84A and 84B. FIG. 84A shows a display on a display screen of the display device 3 when information is input, and FIG. 84B shows an operational flow when the information is input.
Referring to FIG. 84B, the apparatus is powered on, and thereafter a command is input from input device 1 to processing portion 2 through internal data bus 5, so as to activate a program controlling the interconnection and arrangement processing operation (step ST1). In accordance with the activated program, control portion 21 displays necessary menu for processing on the display screen of display device 3. A designer (user) selects a menu displayed on the display screen, and inputs information required by the selected menu through input device 1. Namely, as shown in step ST1 of FIG. 84B, first, description of a circuit cell is required, and the user describes the circuit cell of which arrangement and interconnection are desired (information of the circuit cell is input). Accordingly, as shown in FIG. 84A, circuits cells CC#1 and CC#2 are displayed on the display screen of display device 3. The information input at the time of description of the circuit cell includes the size of the circuit cell (information of lengths in z and Y directions). Thereafter, in accordance with a request from processing portion 2, the designer describes a signal input/output terminal (port) for each of the described circuit cells (step ST2). In accordance with the port description, a state is described in which input terminals P1a, P1b and P1c as well as output terminals P1d and P1e are arranged for circuit cell CC#1. Similarly, description is given for circuit cell CC#2 in which input terminals P2a and P2b and an output terminal P2c are arranged.
Thereafter, connection between ports is described (step ST3). For the input of the connection information, a structure may be used by which the connection information is directly input through the display screen of display device 3 by using a light pen or a mouse, or a structure in which input and output ports are directly described in texture format. By the description of connection between ports, the state is described in which a signal S1 is commonly applied to ports P1a and P2a, signals S2 and S3 are applied to ports P1b and P1c, respectively, a signal S4 is output from P1d to be transmitted to a line or a circuit cell not shown, and a signal S5 from port P1e is applied to port P2b of circuit cell CC#2. Further, it is described that signal S6 is output from port P2c.
After the input of these necessary information is completed, a command instructing the arrangement and interconnection is applied from input device 1 to processing portion 2. In processing portion 2, control portion 21 arranges lines between circuit cells CC#1 and CC#2 in accordance with the information input through input device 1 (stored in data memory 4) and interconnection rule stored in program memory 23.
Control portion 21 executes the following process in step ST4. Namely, control portion 21 extracts information indicative of connecting relation of ports (including circuit cells specifying information) in accordance with the input information, and based on the extracted port connection information, generates information of main lines (lines in X direction) and information on sub lines (lines in Y direction).
FIG. 85 shows an example of the structure of main line and sub line information. Referring to FIG. 85, connection information 130 of one main line includes a main line identifier 131 for identifying a main line uniquely allotted to the main line, and information 132 on sub lines to be connected to the main line. Sub line information 132 includes information of one or a plurality of sub lines. Sub line information 132 includes a sub line identifier 133 for specifying a sub line, and connection information 134 of the sub line. Sub line identifier 133 is uniquely allotted to a sub line. Connection information 134 includes port information 135 specifying a port to which a sub line is connected, and a contact information 136 of a main line to which the sub line is to be connected. Port information 135 includes a circuit cell specifying information. Contact information 136 includes positional information of Y direction on main line. Port information 135 also includes positional information of X and Y directions. After these data are extracted, control portion 21 shown in FIG. 83 performs arrangement and connection of lines in accordance with the processing procedures shown in FIG. 86. The method of arrangement and connection of lines will be described with reference to FIG. 86.
First, in accordance with the described circuit cell and port information, ports are rearranged with respect to each of the circuit cells (step ST10). According to a conventional design rule, in the re-arrangement of ports, ports of the circuit cells are arranged on a side opposing to the line band (on both opposite sides of the circuit cell along the Y direction). Therefore, the described ports are arranged on the upper or lower side along the Y direction, in accordance with the position on the circuit cell.
Thereafter, in the line region determined in accordance with the arrangement of the circuit cell, necessary number of main lines (lines in X direction) are arranged (step ST12). Each main line is identified by main line identifier 131. In accordance with sub line information 132, sub lines are arranged (step ST14). At this time, each sub line is identified by sub line identifier 133. However, if port information 135 includes a port of a circuit cell belonging to different circuit cell band, or if contact information 136 includes contact information of a different main line, then it is determined that the sub line should form a feed through, so that a new main line is added, and sub line and feed through are connected to the added main line. This identification is realized in the following manner. Positional information of X and Y directions are included in the port information. More specifically, when ports are arranged, positional information of X and Y directions are added to each of the ports, and the added positional information of the ports is stored in port information 135 included in connection information 134. Contact information 136 also includes positional information of main line identifier (or position in Y direction) and X direction. Therefore, whether or not a feed through is to be generated is determined.
After main lines and sub lines are arranged, unnecessary lines are deleted (step ST16) in the following way: contact information 136 is tracked for each main line, and the unnecessary main line is removed in accordance with the positional information of X direction included in the contact information. As for the deletion of unnecessary sub line, unnecessary portion of the sub line is removed, so that the sub line terminates at the contact portion. If removal of the unnecessary lines results in an empty region in the line band, and if a line may be arranged in the empty region by shifting the position of the line, the lines are re-arranged.
FIG. 87 shows connection of interconnected circuit cells. The circuit connection shown in FIG. 87 corresponds to the input formation shown in FIG. 84A. Ports of circuit cells CC#1 and CC#2 are arranged at portions in contact with the line region. Referring to FIG. 87, signal line S1 is connected to port P1a through main line S1X and sub line S1Ya, and to port P2a through main line S1X and sub line S1Yb. Signal line S2 is connected to port P1b through main line S2X and sub line S2Y. A signal line S4 connected to port P1d is represented by sub line S4Ya, main line S4X and sub line S4Yb. Signal line S3 is connected to port P1c, through main line S3X and sub line S3Y. Signal line S5 is constituted by sub line S5Ya connected to port P1e, a sub line S5Yb connected to port P2b, and main line S5X interconnecting these sub lines S5Ya and S5Yb. Signal line S6 is implemented by sub line S6Y connected to port P2c, and a main line S6X connected to sub line S6Y. Referring to FIG. 87, main lines denoted by the dotted lines are line portions which are removed in the step of removing unnecessary lines shown in FIG. 86 (step ST16). After the portions denoted by the dotted lines are removed, main lines are re-arranged.
As already described, in accordance with the rule that ports of the circuit cells are arranged at portions in contact with the line bands, a feed through line S4Yb is first connected to main line S4X, and then connected to port P1b through sub line S4Ya. Therefore, sub line S4X used only for arranging the feed through (sub line S4Yb) is arranged, which increases the area occupied by the line band.
Size of a circuit cell differs dependent on a function implemented by the circuit cell. Now, referring to FIG. 88, consider a circuit cell band in which circuit cells CC#A and CC#B having different lengths in Y direction are arranged. According to the conventional rule of arrangement and interconnection, line bands ARA and ARB are arranged on external regions along the Y direction of circuit cell CC#B having the longest direction in Y direction. This is because passage of main lines over the circuit cells is inhibited. Therefore, in such a case, there would be regions NUR on which lines are not arranged, on both sides of circuit cells CC#A in the Y direction, which circuit cell is short in Y direction. This hinders efficient use of the chip area.
FIG. 89 schematically shows an internal structure of a circuit cell CC. Referring to FIG. 89, circuit cell CC includes N well NW for implementing a p channel MOS transistor arrangement region PT, and a P well PW for implementing an n channel MOS transistor arrangement region NT. In N well NW, impurity regions (active regions) PR1 to PR4 for forming p channel MOS transistors are arranged aligned in one line. In impurity regions PR1 to PR4 for forming p channel MOS transistors, gate electrode lines PG1 to PG4 are arranged, respectively. On N well NW, a power supply line VCC formed by the second layer of aluminum interconnection is arranged crossing the gate electrode layer.
In P well PW, impurity regions NR1 to NR4 for forming n channel MOS transistors are arranged. The impurity regions NR1 to NR4 for forming MOS transistors are arranged aligned with the impurity regions PR1 to PR4 for forming MOS transistors provided in N well NW. For impurity regions NR1 to NR4 for forming MOS transistors, gate electrodes NG1 to NG4 are arranged aligned with gate electrodes PG1 to PG4, respectively. On P well PW, a ground line GND formed by the second layer of aluminum interconnection is arranged, in a direction crossing the gate electrodes NG1 to NG4.
In the mutually opposing peripheral regions of N well NW and P well PW, a P well collar PCR and an N well collar NCR formed by highly doped impurity regions are provided. P well collar PCR is formed by a P type impurity region having high impurity concentration, and N well collar NCR is formed by an N type impurity region having high impurity concentration. These collars NCR and PCR are arranged continuously extended along peripheral regions of N well NW and P well PW, respectively, and apply a prescribed potential to corresponding wells. In circuit cell CC, in order to connected transistors to each other and to perform signal input/output from and to the outside of the circuit cell, inner lines HV formed in the first layer of aluminum interconnection are arranged.
FIG. 90A schematically shows a cross sectional structure of the MOS transistor forming region shown in FIG. 89, and FIG. 90B shows an electrical equivalent circuit of a parasitic thyristor formed in N well NW and P well PW.
Referring to FIG. 90A, on a P type semiconductor substrate SB, P well PW and N well NW are formed. In order to separate P well PW and N well NW from each other, a field insulating film LOC formed of a thermal oxide film, for example, is formed in the boundary between the P well and N well. Adjacent to the field insulating film LOC, in P well PW, P well collar PCR formed of highly doped P type impurity region is formed, and in N well NW, N well collar NCR formed by highly doped N type impurity region is arranged.
On the surface of P well PW, an N type impurity region NR (generally referring to NR1 to NR4) for forming n channel MOS transistors is formed. On the surface of N well NW, highly doped P type impurity region PR for forming p channel MOS transistors is formed. Gate electrode layers are not shown.
In the structure shown in FIG. 90A, an npn bipolar transistor Q1 is parasitically formed, in which P well PW serves as a base, N type impurity region NR serves as an emitter and the semiconductor substrate SB serves as a collector. In N well NW, a pnp bipolar transistor Q2 is parasitically formed, in which P type impurity region PR serves as an emitter, N well NW serves as a base and semiconductor substrate SB serves as a collector. The base of the parasitic bipolar transistor Q1 is connected to P well collar PCR through well resistance rs, and receives a constant bias voltage VS (a voltage generally lower than the ground potential). Collector of the parasitic bipolar transistor Q1 is connected to the base of parasitic bipolar transistor Q2. The base of parasitic of bipolar transistor Q2 is connected to N well collar NCR through well resistance rw. To the N well collar NCR, a constant bias voltage (generally a voltage level higher than the power supply voltage) VC is applied.
As shown in FIG. 90B, pnp bipolar transistor Q2 receives the bias voltage VC at its base through resistance rw, and receives the power supply voltage VCC at its emitter through impurity region PR. Meanwhile, parasitic bipolar transistor Q1 has its emitter connected to the level of the ground potential through N type impurity region NR, and receives at its base the bias voltage VS through resistance rs. For simplicity of description, assume that the bias voltage VC is equal to the power supply voltage VCC and the bias voltage VS is equal to the ground voltage (denoted by the dotted lines in FIG. 90B). In this case, bipolar transistors Q1 and Q2 constitute a thyristor.
A state in which parasitic thyristor shown in FIG. 90B is rendered conductive is generally referred to as "latch up phenomenon." The latch up phenomenon is triggered by a changing current incidental to fluctuation of power supply voltage, a punch through current at a well boundary, and so on. Such current serves as a trigger current introduced to the base terminal of the parasitic thyristor circuit shown in FIG. 90B. When a trigger current is generated in P well PW, the current flows through resistance rs, and voltage drop across the resistance rs turns on the bipolar transistor Q1. When bipolar transistor Q1 turns on, collector current of bipolar transistor Q1 flows through resistance rw and bias power supply VC. When the base-emitter of bipolar transistor Q2 is biased in forward direction, the bipolar transistor Q2 turns on. When bipolar transistor Q2 turns on and collector current of bipolar transistor Q2 flows, the collector current flows through resistance rs, and further increases the base potential of bipolar transistor Q1 which has already been turned on. Consequently, the collector current of bipolar transistor Q1 is again increased, driving bipolar transistor Q2 more deeply on.
As a result, bipolar transistors Q1 and Q2 are completely turned on, and a large current flows from the bias power supply VC to the bias voltage VS. Such latch up phenomenon is generated when one of the bipolar transistors Q1 and Q2 is biased in the forward direction and the other has its base-emitter biased in the forward direction. The trigger current may be generated by a noise in P well PW or N well NW. Generation of a trigger current is suppressed to prevent the latch up phenomenon by providing P well collar PCR and N well collar NCR so as to fixedly set the potentials of P well PW and N well NW.
However, as shown in FIG. 89, when P well PW and N well NW are both provided with collars PCR and NCR, a problem that the latch up resistance becomes lower than when only one collar is arranged on one well region, arises.
FIG. 91 shows relation between the arrangement of collars and the hold voltage VH at the time of a latch up. In FIG. 91, the abscissa shows distance (by the unit of .mu.m) between impurity regions formed in the well, and the ordinate represents holding voltage Vh.
Referring to FIG. 92A, the distance between the P+-N+ represents the distance between N type impurity region formed in a P well and a P type impurity region formed in an N well. Referring to FIG. 92B, holding voltage Vh represents a voltage applying a hold current Ih when the parasitic thyristor circuit turns on.
FIG. 91 shows holding voltages when a P well collar is arranged on the P well region, the collars are arranged on both P and N wells, and when the collar is not provided, obtained through experiments by the inventor. The higher the value of the holding voltage Vh, the higher the voltage at which the parasitic thyristor is turned on, that is, the smaller the possibility of latch up phenomenon. More specifically, it can be seen from FIG. 91 that when a collar is provided only on the N well, latch up resistance is higher than when collars are provided for both P and N wells. Therefore, when collars are arranged on the N well and P well opposing regions in order to suppress generation of a trigger current both in the P well and N well, immunity to latch up phenomenon becomes inferior conversely. Here, the collars are arranged in the periphery of opposing regions of P well and N well in order to make smaller the values of resistances rw and rs shown in FIG. 90B, so that the collars can also function as guard rings.
Collars NCR and PCR are arranged continuously extending along the peripheral regions of N well NW and P well PW. In this case, in order to connect gates of p channel MOS transistors and n channel MOS transistors, it is necessary to use the first layer of aluminum interconnection HV as shown in FIG. 89. When the gates of p channel and n channel MOS transistors are connected to each other by using a gate interconnection layer, impurity regions are formed in self alignment with respect to the gate electrode and therefore in N well collar NCR and P well collar PCR, MOS transistors would be formed. In that case, since impurity region is not formed below the gate electrode layer of collars NCR and PCR, the MOS transistors in collars NCR and PCR are rendered conductive dependently on the signal potential on the corresponding gate electrode layer. Therefore, in this case, there is not an adverse effect on the function of applying a bias voltage of the collars NCR and PCR. However, there is provided an additional MOS transistor formed to the gate electrode layer, so that additional gate capacitance is provided to the gate electrode layer, parasitic capacitance of the signal lines increases resulting in delay in signal propagation, which leads to degradation of the circuit performance. Therefore, a gate electrode layer cannot be formed across the collars NCR and PCR. For this reason, in order to connect gate electrodes of p channel and n channel MOS transistors to each other as shown in FIG. 89, another line such as the first layer of aluminum interconnection HV must be used, another first layer of aluminum interconnection cannot be arranged additionally in this region, and hence degree of freedom in interconnection is decreased.
In addition, N collar NCR can not be made contact with P collar PCR because the reverse breakdown voltage of P+/N+ junction structure is low. Thus, P well PW and N well NW are formed being isolated from each other, and there is a space between P well PW and N well NW, and the cell size can not be reduced.
Further, a circuit cell includes one p channel MOS transistor arrangement region PT and one n channel MOS transistor arrangement region NT. In this case, it is possible to optimize the arrangement of p channel MOS transistor and n channel MOS transistor in the circuit cell. However, in the semiconductor integrated circuit device, there are a plurality of circuit cells arranged aligned with each other, and these plurality of circuit cells are connected to each other. Therefore, signal input/output nodes of circuit cells CC must be arranged taking into consideration connection with other circuit cells. However, if the arrangement of the transistors in a circuit cell is optimized in accordance with the input/output port A of the circuit cell CC, it becomes quite difficult to change the positions of ports to optimize connection with other circuit cells while maintaining the original optimal arrangement. Therefore, in this case, referring to FIG. 93, when a signal on main line La is to be input to or output from a signal input/output port A of circuit cell CC, it becomes necessary to connect the input/output port A and main line La by means of a feed through FT and another main line Lb. Therefore, in this case, optimization of the arrangement of lines taking into considerations the lines (external lines) of the semiconductor integrated circuit device as a whole is not possible, the feed through FT is necessary, increasing the area occupied by the lines, and the size of the semiconductor integrated circuit device as a whole becomes large.